1. Field of the Invention
The present invention relates to a semiconductor memory device of a type from which stored data is read out, such as Read-Only Memory (ROM) and Erasable and Programmable Read-Only Memory (EPROM).
2. Description of the Related Art
FIG. 8 is a circuit diagram showing the structure of a conventional ROM device 100. This ROM device 100 is a mask ROM in which data is programmed preliminarily when the mask is produced and comprises memory cells M00-M0n, M10-M1n, bit line BL0 connected to the memory cells M00-M0n, bit line BL1 connected to the memory cells M10-M1n and word lines WL0-WLn connecting a row selecting transistors of the respective memory cells in the row direction (horizontal direction in FIG. 8). The memory cell M00 includes a row-selecting transistor TR00 whose source is connected to the bit line BL and a data switch SW00 whose an end is connected to a drain of the row selecting transistor TR00. The data switch SW00 is so constructed that the other end is opened or connected to VSS depending on a mask pattern upon manufacturing.
A pre-charge switch SWP0 and a column selecting switch SWC0 are connected to the bit line BL0. Other bit line such as the bit line BL1 has the same structure as the bit line BL0. The other end of the column selecting switch SWC0 is connected to an input of a sense amplifier AMP as well as the other end of the column selecting switch connected to the other bit line.
The column selecting switch is controlled by conduction of a corresponding column selecting signal. For example, the column selecting switch SWC0 is controlled to be conductive when a column selecting signal CL0 changes to low level. The corresponding column selecting signals are controlled to be excluded for each bit line. As a consequence, if a specific column selecting signal is activated, the level of a corresponding bit line is transmitted to the input of the sense amplifier AMP.
Next, the reading operation of the ROM device 100 will be described.
Upon standby for reading out, with the word lines WL0-WLn maintained at the low level, pre-charge control signal BLR is turned to low level. As a consequence, the pre-charge switches SWP0-SWPm become conductive so that the parasitic capacities of the bit lines BL0-BLm are charged to high level (this operation is called pre-charge of bit line).
The read-out can be carried out by changing a word line corresponding to a memory cell from which data is to be read out and changing a corresponding column selecting signal to low level.
When reading out data of the memory cell M00, the row selecting transistor TR00 and the column selecting switch SWC0 become conductive by changing the word line WL0 to high level and the column selecting signal CL0 to low level so that low level is outputted to the input of the sense amplifier AMP.
As a related ROM device, technologies disclosed in Japanese unexamined patent publication No. H9(1997)-7382 and Japanese unexamined patent publication No. 2004-158111 can be mentioned.